The present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device having a gate insulating film including a high dielectric material and a method for fabricating the same.
With the recent increase in the integration and speed of semiconductor devices, metal oxide semiconductor field effect transistors (MOSFETs) are being increasingly miniaturized. As the gate insulating film of the transistors becomes thinner and thinner along with this miniaturization, problems such as increase in gate leakage current due to a tunnel current will come to the surface. To solve this problem, it has been examined to use, as the gate insulating film, a high dielectric (high-k) film made of any of hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), etc. which have a dielectric constant higher than silicon oxide (SiO2) and silicon nitride (Si3N4), thereby to increase the physical thickness of the gate insulating film. Incidentally, it has also been examined to use a metal gate electrode to prevent generation of a deletion layer, which is generated in a polysilicon layer when the polysilicon layer is used as the gate electrode.
In use of a metal gate electrode, the metal gate electrode must exhibit a level of work function with which an appropriate threshold voltage is secured for an n-type metal insulator semiconductor (MIS) transistor or a p-type MIS transistor, at the interface with the gate insulating film, for reduction in power consumption. In recent years, a gate insulating film containing lanthanum (La) is formed for n-type MIS transistors, and a gate insulating film containing aluminum (Al) is formed for p-type MIS transistors, to satisfy the above requirement.
A conventional method for fabricating a semiconductor device using a high-k film and a metal gate electrode will be described with reference to FIGS. 13A-13F, 14A-14F, and 15.
As shown in FIG. 13A, a p-type region 102 and an n-type region 103 are formed in an upper portion of a semiconductor substrate 101 made of silicon (Si) by ion implantation, etc. Subsequently. an element isolation film 104 as a silicon oxide film is formed in a boundary region between the p-type region 102 and the n-type region 103.
As shown in FIG. 13B, a silicon oxide (SiO2) film 105A and a polysilicon film 106A are sequentially formed on the p-type region 102, the n-type region 103, and the element isolation film 104.
As shown in FIG. 13C, dummy gate insulating films 105 and dummy gate electrodes 106 are respectively formed from the SiO2 film 105A and the polysilicon film 106A by etching.
As shown in FIG. 13D, using the dummy gate electrodes 106 as a mask, n-type impurity ions and p-type impurity ions are respectively implanted in the p-type region 102 and the n-type region 103, to form extension layers 107 and 108.
A shown in FIG. 13E, a silicon nitride (SiN) layer is formed to cover the semiconductor substrate 101, the dummy gate insulating films 105, and the dummy gate electrodes 106 and then etched back, to form gate sidewall insulating films 109.
As shown in FIG. 13F, using the dummy gate electrodes 106 and the gate sidewall insulating films 109 as a mask, n-type impurity ions and p-type impurity ions are respectively implanted in an upper portion of the p-type region 102 and an upper portion of the n-type region 103 and then heat-treated, to form source/drain regions 110 and 111.
As shown in FIG. 14A, silicide layers 112 and 113 made of nickel silicon (Nisi) are formed in upper portions of the source/drain regions 110 and 111 by a known silicide formation technique.
As shown in FIG. 14B, an interlayer insulating film 114 made of SiO2 is formed to cover the semiconductor substrate 101, the dummy gate electrodes 106, and the gate sidewall insulating films 109, and then polished by chemical mechanical polishing (CMP), etc. until the dummy gate electrodes 106 are exposed.
As shown in FIG. 14C, the dummy gate electrodes 106 are selectively removed by dry etching, and then the dummy gate insulating films 105 are removed by wet etching, thereby forming a first gate embedding groove 115 on the p-type region 102 and a second gate embedding groove 116 on the n-type region 103.
As shown in FIG. 14D, a mask film 117 as a silicon film having a thickness of about 1 μm is formed on the interlayer insulating film 114 so as to fill the first gate embedding groove 115 therewith but not to fill the second gate embedding groove 116.
As shown in FIG. 14E, an amorphous lanthanum aluminum oxide (LaAlO3) film that has a thickness of about 3 nm and a concentration ratio of Al to La of 1.5 is formed on the mask film 117 and at the bottom of the second gate embedding groove 116 that is on the n-type region 103, as a gate insulating film 118 for a p-type MIS transistor, by CVD, sputtering, or the like.
As shown in FIG. 14F, after removal of the Si mask film 117, an amorphous LaAlO3 film that has a thickness of about 3 nm and a concentration ratio of Al to La of 1.0 is formed at the bottom of the first gate embedding groove 115 that is on the p-type region 102, as a gate insulating film 119 for an n-type MIS transistor, in a manner similar to that for formation of the gate insulating film 118. An Si mask film used for this formation is then removed.
As shown in FIG. 15, gate electrodes 120 and 121 made of tantalum carbide (TaC) are formed on the gate insulating films 118 and 119 by a known method, thereby to obtain a conventional semiconductor device.
In the semiconductor device fabricated by the conventional fabrication method described above, the concentration ratio of Al to La in the gate insulating film of the p-type MIS transistor is larger than that in the gate insulating film of the n-type MIS transistor, thereby to secure appropriate threshold voltages (see Japanese Patent Publication No. 2009-117557, for example).
As described above, the threshold voltage shifts in the opposite directions due to La and Al that are metals for adjusting the threshold voltage to an appropriate value. This phenomenon occurs because the polarities of the fixed charge brought about in the gate insulating film by La and Al are the opposite to each other. More specifically, for an Al-rich film, negative fixed charge occurs at the interface between the substrate and the gate insulating film, resulting in shift of the flat band voltage to the positive side, while, for a La-rich film, positive fixed charge occurs at the interface between the substrate and the gate insulating film, resulting in shift of the flat band voltage to the negative side.
With the mechanism described above, a semiconductor device having appropriate threshold voltages can be implemented by changing the concentration ratio of Al to La in the gate insulating film.